This invention relates generally to semiconductor manufacturing processes and more particularly to semiconductor manufacturing processes suitable for use in integrated circuit fabrication.
As is known in the art, with the need for smaller, faster and in general more versitile integrated circuit performance, two trends are emerging in micro-electronic devices. One is a configurable interconnect array scheme wherein a plurality of gates are electrically interconnected through fusable links, for example, and wherein the array is customized by the purchaser by open circuiting selected ones of the fusable links to provide the desired configuration. The second technique is sometimes referred to as "customizing a master slice". In the second technique, an array of unconnected logic gates is initially fabricated and the gates in the array are then selectively interconnected during the final metallization process. This customization procedure is called personalization of configurable gate arrays.
As is also known in the art, any reduction in the number of masking steps required in the fabrication of the configurable gate array results in cost savings because of the elimination of the manufacturing step and the added electrical device yield increase that results from not introducing any additional yielded detracting effects associated with that additional processing step. Further, as the switching times of the gates are reduced, the need for the associated reduction in contact metallization penetration into the shallow junctions associated with such faster switching gates is required. Historically, metallization contact penetration into these junctions has not been a severe problem because of relatively loose design rules which may be tolerated with lower density arrays. Currently, however, the need for micro-electronic devices having shallow contacts are essential in order to achieve a well-controlled interfacial reaction with a device semiconductor material, typically silicon. Device reliability and ultimate catastrophic failure will be predominantly controlled to a large extent by the manner in which the metalization contacts are formed on the silicon. In bipolar structures, the emitter and base regions would typically be the most sensitive to the metallization contact-silicon interface reaction. The metallization contact-silicon interface is particularly critical when a Schottky contact is formed.
One technique suggested to fabricate a bipolar semiconductor device has been to first form a base diffusion in a silicon epitaxial layer formed on a semiconductor substrate. A silicon dioxide layer is then formed on the surface of the epitaxial layer. A mask process is used to form a window through a portion of the silicon dioxide layer disposed over the portion of the base diffusion region where the emitter region is to be formed. A suitable dopant is diffused through the window into the base diffusion region to form the emitter region. A second window is formed in the silicon dioxide layer over the region of the epitaxial layer where a Schottky contact metallization is to be formed. A second layer of silicon dioxide is deposited over the previously formed silicon dioxide layer and over the areas of the epitaxial layer exposed by the windows. A layer of silicon nitride is then deposited over the second silicon dioxide layer. A third layer of silicon dioxide is then deposited over the layer of silicon nitride. The process then continues by forming a window through the third silicon dioxide layer, the silicon nitride layer, and the first and second silicon dioxide layers using an oversized photoresist mask to expose the region where the Schottky contact is to be formed. A suitable metal such as platinum is deposited over the surface of the structure and through this later formed window onto the exposed portion of the epitaxial layer. The structure is then heated to form a platinum silicide Schottky contact with the remaining portion of the platinum being chemically removed. A second oversized mask having a window over the emitter contact region is then used to remove the third silicon dioxide layer, the silicon nitride layer and the first and second silicon dioxide layers to expose the emitter contact region. It should be noted that with this process prior to the formation of the platinum silicide Schottky contact, a layer of silicon dioxide is disposed on the portion of the silicon epitaxial layer where the platinum silicide Schottky contact is to be subsequently formed. Because the thermal expansion coefficient of the silicon is different from that of the silicon dioxide, crystal dislocations in the silicon region where the platinum silicide Schottky contact is to be formed causes the subsequently deposited platinum to grow in fault lines in the silicon with the result that after forming a platinum silicide contact in such region of the silicon, large reverse bias fields which lower the breakdown voltage of the Schottky contact result, and since this effect is random and not readily predictable, the performance reliability of the device is adversely affected. It should also be noted that this process requires that the etchant used to remove selected portions of a silicon nitride layer in exposing the emitter contact region also contacts the previously formed platinum silicide Schottky contact. The etchant used is hot phosphoric acid and the use of such etchant has the concommitant effect of also attacking the previously formed platinum silicide.